| 摘要 |
PURPOSE:To realize a large capacity address space with plural memory planes by designating one of plural memory planes corresponding to an X address and a Y address. CONSTITUTION:By a mode 1 assigning two-dimensional memory planes 11-0-11-3 of 512X512 dots to the same address space, selecting instruction information MS set at a memory selecting register 12 is inputted through a selector 16 to a decoder 17 and an objective memory plane is designated. On the other hand, in a mode 2 to combine the memory planes 11-0-11-3 and realize the two-dimensional space of 1024X1024 dots, the high-order bit of an X address counter 14 and a Y address counter 13 is inputted through the selector 16 to the decoder 17. Thus, one memory plane is designated corresponding to an X address and a Y address and a large capacity address space is realized.
|
