发明名称
摘要 PURPOSE:To display the vertical direction in a smooth form, by carrying out an artificial interlace in terms of L pieces of data which are read out with overlap in case a video signal is written into a memory and then reading the video signal to enlarge it by L times for display. CONSTITUTION:A read control signal is supplied to a shift register (a) and then shifted by the clock of a horizontal synchronizing signal HD to produce shift outputs QA, QB.... The read-out clock shifted by 1H is turned into the output QB, and a delay of 1/2L-1L can have the correspondence by selecting each of the shift outpus of QA, QB... regardless of the value of L. This output is used by being switched to the original read control signal in the 1st field and to the above-mentioned shift output in the 2nd field respectively through a fieldswitching circuit (b). The circuit (b) carries out a switching operation by applying the outpus Q and Q' of an FF using a vertical synchronizing signal VD as its input to tristate buffers C1 and C2. In such way, a smooth display is possible for the video signal which is read out of a memory.
申请公布号 JPS6343950(B2) 申请公布日期 1988.09.01
申请号 JP19810041204 申请日期 1981.03.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YASUMOTO YOSHIO;FUJITA MASAAKI
分类号 H04N5/262;G09G5/36;H04N7/01 主分类号 H04N5/262
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