| 摘要 |
PURPOSE:To improve the reliability of the titled circuit by providing a timing circuit bringing a gate potential of an NMOS transistor (TR) provided between a power supply and an output terminal is brought into a high level after the output boosting. CONSTITUTION:With an input signal changed from a high level to a low level, the potential of the output signal is boosted to a power potential or over by the output of a CMOS inverter 1. While the potential of a gate N2 of the TR Q2 is kept to a low level, when the boosting is finished, the potential goes to a high level by a timing circuit 10. If a TR Q3 is turned on momentarily, the potential of the output signal is deceased and the gate-source voltage of the TR Q2 reaches the threshold voltage, the TR Q2 is turned on and the output terminal is charged. Then the potential of the gate N2 of the TR Q2 rises over the power potential and the potential of the output signal is kept to the power potential. Thus, the output level is compensated and the reliability of the circuit is improved.
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