发明名称 CYCLIC DIGITAL FILTER
摘要 PURPOSE:To prevent the oscillation at a limit cycle by providing a 1st round means used when a feedback path output is fed to an input signal even when a signal having a DC component is inputted to a cyclic digital filter having the feedback path and a 2nd round means at a multiple of (1-a) by a 2nd multiplication circuit so as to apply different rounding operation. CONSTITUTION:The 1st rounding means rounds down a signal in the case of the relation of epsilon<q (epsilon1 is a value less than the effective digit, 0<epsilon1<1 and q is a threshold with a relation of 0<=q<=1) and rounds up the signal in case of epsilon1>=q, when the minimum identification quantity represented by the effective digit of the signal is the unity. Moreover, the 2nd rounding means is provided, which rounds the signal to the effective digit when the value of the signal less than the effective digit is not zero by a multiplication circuit 12. The 2nd rounding means rounds down a signal in the case of the relation of epsilon2<(1-q) (epsilon2 is a value less than the effective digit, 0<epsilon2<1 and 1 is a threshold with a relation of 0<=q<=1) and rounds up the signal in case of epsilon2>=(1-q), when the minimum identification quantity represented by the effective digit of the signal is the unity. Thus, the oscillation caused by the limit cycle is prevented.
申请公布号 JPS63204810(A) 申请公布日期 1988.08.24
申请号 JP19870036087 申请日期 1987.02.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHINO SHOICHI;HASHIMOTO SEIICHI
分类号 H03H17/04;G06F7/48 主分类号 H03H17/04
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