| 摘要 |
To test an integrated circuit such as in Fig 1 wherein there are different paths with different delays between input test registers R1, R2 and output test registers R3, the different delays preventing exhaustive test patterns from being applied to internal embedded combinational blocks Ca, Cb, the serial path of shift registers has additional registers Ds(Fig 2) to resynchronise the test patterns for the logic blocks. Alternatively, the serial path is considered to have imaginary delays present and non-contiguous inputs to the logic blocks are stimulated by exhaustive test patterns provided by a special algorithm viz a polynomial functionally dependent on the difference in the delays along the signal paths. The technique may be used with interleaved test registers. <IMAGE> |
