| 摘要 |
<p>PURPOSE:To detect whether or not a recovered clock and an input data are synchronized by returning a count to a prescribed value when a code change point signal is not within a range for a prescribed time and generating a synchronizing detection signal when the count value reaches the prescribed value. CONSTITUTION:When a code change point signal 1200 is not in the timing within + or -1/8T, the signal is given to an AND circuit 52, goes to a signal 90 and given to a clear terminal CL of a shift register 61 of a counter circuit 6. Thus, when the recovered clock 400 is not synchronized with a reception data 100, the signal 900 is outputted from the AND gate 52 to clear a register 61. That is, an output signal from an output terminal QH of the 8-th stage of the register 61 is used as the bit synchronizing detection signal 200, then the signal 200 is zero when the recovered clock 400 is not synchronized with the reception data. So long as the signal 1200 is within + or -1/8T and the recovered clock 400 is synchronized with the reception data 100, the synchronizing detection signal 200 being an output of the register 61 remains logical 1.</p> |
