| 摘要 |
PURPOSE:To stably reproduce a data by detecting the lead/lag a timing pulse to a digital signal and using a phase shifter so as to correct the result thereby identifying the result at the center of the data pulse at all times. CONSTITUTION:A data of a data input terminal 1 is inputted to a terminal A or B and an output pulse from a phase shifter 3 is inputted to a CLR terminal. In this case, a timing pulse is inputted through an inverter 9 to monostable multivibrators 7, 8. The signal is inputted to OR gates 10, 11 from the monostable multivibrators 5 and 6, and 7 and 8 respectively and subjected to OR processing and the outputs of the gates 10, 11 are given to an inverting integration device 14 through an inverting buffer amplifier 12 and a noninverting buffer amplifier 13 and the output is used as a control voltage of said phase shifter 3. Thus, the control voltage of the phase shifter is set so that the data is identified at the center of data pulse. |
