发明名称 TIMING EXTRACTING CIRCUIT
摘要 <p>PURPOSE:To reduce the number of constitution components, by generating a pulse string including a sine wave component with a cycle of 1/T by operating an FF at the time of inverting the polarity of a CMI signal from a low level to a high level. CONSTITUTION:An input CMI signal En sets the FF4 at the time of inverting the signal from the low level to the high level, and a pulse rises at the output of the FF4. Afterwards, after the lapse of a time T/2, the FF4 is reset by a delay signal En' that is the output of a delay circuit 3, and the pulse rises at the output of the FF4. In such a way, the pulse string Fn including the sine wave component of cycle T is generated at the output of the FF4. lt is possible to obtain the sine wave of cycle T at an output terminal 2 by passing the pulse string Fn through a band-pass filter 5.</p>
申请公布号 JPS63189029(A) 申请公布日期 1988.08.04
申请号 JP19870020536 申请日期 1987.02.02
申请人 NEC CORP 发明人 RIKIYAMA HIROKI
分类号 H04L7/00;H04L7/02;H04L7/027 主分类号 H04L7/00
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