发明名称 AUTOMATIC DIAGNOSING SYSTEM FOR PARITY CIRCUIT
摘要 PURPOSE:To realize automatic diagnosis by program control, by constituting a system so that the generation and the control of a parity error can be performed by a register operation from a processor. CONSTITUTION:At the time of diagnosing, a gate G3 is closed, and after a gate G2 is set at an exclusive OR state, the processor MPU accesses to a bus targeted to be diagnosed. A write data from the MPU is sent to a bus BUS, and also, is inputted to a parity generator PGE, and a parity bit is generated, however, it is inverted at the gate G2, and is inputted to a buffer BUF. A parity checker PCH performs parity check based on the write data and the buffer BUF. Since the parity bit is inverted by the gate G2, the parity error is generated in a normal operation, and is fetched in a register REG3, and at a state where the gate G3 is opened, it is fetched in the MPU, then, is used for diagnosis.
申请公布号 JPS63184139(A) 申请公布日期 1988.07.29
申请号 JP19870016655 申请日期 1987.01.27
申请人 FUJITSU LTD 发明人 MATSUBARA SATOSHI
分类号 G06F11/08 主分类号 G06F11/08
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