| 摘要 |
PURPOSE:To decrease compensation error by using an SC integration device applying inverting or noninverting integration in response to the result of comparison between a reference voltage and an output signal of a two-input analog adder so as to generate a compensation signal whose absolute value in the positive and negative directions is equal to each other. CONSTITUTION:When an output signal of an amplifier circuit 2 is larger a reference voltage Vr1, the output of a comparator circuit 4 goes to 'H', pulses phi1, phi2 are generated from a four-control signal generating circuit 1 and pulses phi3, phi4 are generated after being delayed by a delay circuit 15. Thus, the SC (switched capacitor) integration device 13 applies the inverting integration and a negative compensation signal DELTAVc<->=(Cs/C1).Vr2 is generated. Thus, the output of the two-input analog adder 4 is changed by DELTAVc<-> and the operation above is repeated when the change is larger than the voltage Vr1. When the output signal of the adder 4 is smaller than the voltage Vr1, the pulses phi1, phi3 are generated and then the pulses phi2, phi4 are generated. Thus, the integration device 13 generates a positive compensation signal DELTAVc<->=(Cs/C1).Vr2 and the output of the adder 4 is shifted positively by DELTAVc<->. Thus, the absolute value of the difference between the output signal and the Vr1 after compensation is at maximum (Cs/C1)XVr2. Thus, the error is halved in comparison with a conventional amplifier.
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