| 摘要 |
PURPOSE:To effectively fetch by sending addresses in parallel to a main memory from two ports when both blocks of the first half data and the second half data are not stored yet in block cross. CONSTITUTION:The access address and the length of the request data received from a requester are inputted to an address register and a block cross deciding circuit 4. In this case, the circuit 4 detects the request of an operand covering the block of a buffer memory and both a tag 7 and a comparator 8 are unable to find out the first half data block in the buffer memory 6. Under such conditions, a request is produced from a port 9 to a main memory. Furthermore the address of the next block is formed in the register 1 and a request is produced to the main memory from an address port 10 when it is discriminated that the block including the second half data is not included in the memory 6 either.
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