| 摘要 |
<p>PURPOSE:To set an optimum oscillating stable time and to use a stabilized oscillation output, by providing a means for selecting a desired one output out of a plurality of delayed outputs of a prescaler connected to an output of an oscillator. CONSTITUTION:Data representing a stabilized time of an oscillator 10 determined in response to a frequency used at a processor are set to a selection register 16. A standby start signal is applied to an inverter 12 via an OR circuit 14 afterward and a clock oscillator 10 is stopped, a frequency divider 13 which is a prescaler is reset and a signal 0 is applied to a terminal S. In applying a standby release signal 1 to the terminal S, the inverter 12 is activated to produce oscillating operation for the oscillator 10, the reset of the frequency divider 13 is released and the count operation of the output of the oscillator 10 is started. When the count is advanced and a frequency division output selected with a data set at the register 16 has level 1, the output is transmitted via a multiplexer 15 and a signal 0 in operation is outputted from a NAND circuit 17.</p> |
