| 摘要 |
PURPOSE:To omit a micro instruction holding mechanism and a micro instruction invalidating circuit by addressing a stored ineffective micro instruction if it is detected that the execution start of a microprogram is kept waiting. CONSTITUTION:When a micro instruction x+n including a micro order END is outputted to an MMEM (microprogram memory) 402, a status signal BSY goes to '1' because a status signal V is '0', that is, the execution start address of a new microprogram is ineffective. At this time, a load signal LDEND is issued, and a constant M is loaded to an MAR (micro instruction address register) 100 after one clock. When one clock elapses furthermore, contents of MMEM 402 corresponding to the micro instruction address M, namely, nop (no operation) instruction is executed. Since a hold signal HOLD is '1' hereafter until the status signal V goes to '1', contents of the MAR 100 are held as the constant M, and the nop instruction is also held in the output of the MMEM 402.
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