| 摘要 |
PURPOSE:To reduce the resistance a source may present by a method wherein an interface between an active layer and buffer layer under a recess slope is located nearer to a substrate than an interface under a gate electrode is. CONSTITUTION:With a gate pattern formed on a GaAs substrate 1 serving as a mask, the GaAs substrate 1 is exposed to a phosphatic etchant for the formation of a ridge. Next, the GaAs substrate 1 is subjected to a surface treatment in a sulfate etchant. A process follows wherein an undoped GaAs layer 2 to serve as a buffer layer, an Si-doped n-GaAs layer 3 to serve as an active layer, an Si-doped n<+>-GaAs layer 4 to serve as a surface n<+>-layer, are grown, in that order, which are all accomplished with help of a molecular beam epitaxy unit. Next, a photoresist is provided for the purpose of flattening, and then etching is accomplished by using an RIE unit. A phosphatic etchant is again used in a process of etching wherein the retained resist pattern serves as a mask, an Al film is formed by evaporation, and then peeling is accomplished in an organic solvent for the construction of an electrode 5. A source electrode 6 and a drain electrode 7 are next constructed. The design decreases source resistance and increases transconductance Gm.
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