| 摘要 |
PURPOSE:To prevent divided transfer data from being misrecognized without applying load to a CPU by selectively opening both port gates of a two-port memory by a memory access deciding circuit. CONSTITUTION:When data A-C are received by a serial transfer control circuit 12, a detecting circuit 15 detects the obtained parallel data as the initial or final transfer data when the specific bit of the data is turned to '0' or '1'. When a read request from the CPU 10 is in an insignificant state such as time t0 and the detecting circuit 15 detects the initial transfer data A, the memory access deciding circuit 17 closes the 2nd port side gate 16b and opens the 1st port side gate 16a. Said status is maintained until the final data B is written in a two-port RAM 13. Even if a reading request is turned to a significant state such as time t1, data reading from the CPU 10 to the RAM 13 is inhibited and the misrecognition of the divided transfer data which may be generated by reading out data on the way of transfer by the CPU 10 can be surely prevented.
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