| 摘要 |
PURPOSE:To shorten a time required for reset, by driving a shift register with two phase clocks being superimposed at the time of resetting in a logic circuit provided with the shift register consisting of plural FFs and a combination circuit. CONSTITUTION:A superimposing two phase clock generating means is formed with a NOT circuit 122, and OR circuits 123 and 124. Consequently, since the level of the terminal CA of the SRL2 is an H when the L of an SRL1 is shifted to an SRL2, the data shifted to the SRL2 is shifted immediately to an SRL3. And hereafter, the same operation is repeated, and so-called lacing is generated. Therefore, the levels of the terminals SO of the SRL1-100 go to the Ls, then, all of the SRLs are reset. Thus, it is possible to shorten the time required for the reset. |
