| 摘要 |
PURPOSE:To reduce the projection of a gate electrode sufficiently by forming a gate opening section at two stages, minimizing parasitic capacitance while applying a fluid substance by using an upper opening and dry-etching a substrate from the vertical direction. CONSTITUTION:Si<+> ions are implanted selectively into a semi-insulating GaAs substrate 11 to shape a semiconductor active layer 12, and an Si3N4 film 13 in thickness of 2000Angstrom and an SiO2 film 14 in thickness of 3000Angstrom are applied onto the surface of the active layer 12 in succession. A photo-resist pattern 15 is formed into a region in which a gate electrode must be shaped, and the film 14 and the film 13 are etched successively to form an opening 52. A photo- resist is removed, and a gate metal 53 consisting of Ti-Pt-Au is evaporated. A photo-resist 16 is applied onto the whole surface, and the resist 16 and the gate metal 53 on the film 14 are removed from the direction vertical to a wafer to form a T-shaped gate 55. Source and drain electrodes 31, 32 are shaped. Accordingly, parasitic capacitance can be reduced while the upper projection of the gate 55 can be scaled down.
|
