| 摘要 |
PURPOSE:To enable measurement of an operating speed with limited capacitance load, by supplying an output of an input buffer to a test output terminal synchronizing a test clock signal. CONSTITUTION:An output terminal 9 is opened and a test mode signal node is shifted to 0 for the test mode. With the test mode signal shifted to 0, a selector comprising AND circuits 4 and 5 and an OR circuit selects a test clock, which operates an internal logic not illustrated to put on FF 7 to 0 or 1 and the test clock is supplied again to set an FF 11. In this manner, while the test clock is being supplied, the total delay time is measured for an output buffer 8, an input buffer 10, the FFs 7 and 11 and an output buffer 14 and subsequently, an enable signal is supplied to close the buffer 8 and a data is supplied from a tester to measure the total delay time for the buffer 10, the FF 11 and the buffer 14. Difference between the two total delay time corresponds to that of the total delay time between the buffer 8 and the FF 7. This enables measurement of operation time free from effect of a load capacitance due to a universal tester.
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