| 摘要 |
PURPOSE:To share a trace memory by providing a trace data selecting circuit which switches data written in the trace memory from a data latch flip flop by the processor processing timing signal or the data selector signal outputted from an emulator processor. CONSTITUTION:Processing timing signals t0 and t1 outputted from an emulator processor 1 through processing timing signal lines 11 and 12 become four low active signals T0, T1, T2, and T3 by a demultiplexer 6, and they are outputted to trace select lines 14, 15, 16, and 17. The CPU status is written in the trace memory in time division at timing of signals T1, T2, and T3, thereby sharing the memory and a trace data line.
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