发明名称 BUFFER CIRCUIT
摘要 PURPOSE:To obtain a circuit operated even with a large load at the output by adding two transistors (TR) of NPN and PNP TRs for transistors at the output terminal in a circuit used for impedance conversion or the like. CONSTITUTION:The base/emitter of the NPN TR 8 are connected to the collector/base of the TR 2 at the output terminal 7 in the buffer circuit, the collector is connected to a power supply VCC, the emitter/base of the PNP TR 9 are connected to the base/emitter of the TR 2 and the collector is connected to ground (GND). In the buffer circuit constituted in this way, when a load larger than a current 11 of a constant current source 5 is connected to the output, since the load current flows to said NPN TR 8 or the PNP TR 9, the circuit operation is attained even when a load larger than the current 11 is connected.
申请公布号 JPS63122307(A) 申请公布日期 1988.05.26
申请号 JP19860268302 申请日期 1986.11.11
申请人 MITSUBISHI ELECTRIC CORP 发明人 IDA SHIZUO
分类号 H03F3/45;H03F3/343;H03F3/50 主分类号 H03F3/45
代理机构 代理人
主权项
地址