发明名称 SERIAL INTERFACE CIRCUIT
摘要 PURPOSE:To obtain the transfer format of arbitrary number of bits with a simple constitution, by constituing a circuit so that an additional clock and an additional data can be sent by the control of a data processing part after the serial transfer of a prescribed number of bits is completed. CONSTITUTION:A data processing part 8 outputs a write pulse to a write signal 11 at a timing t10 by the control of a program, and writes additional data D8-D9 on a shift register 1. Next, it outputs a clear pulse to a clear signal 50 at a timing t11, thereby, clears a clock latch 5, and outputs a low level to a clock latch signal 52. At this time, since a clock signal 20 holds a high level, an SCK signal goes to the low level, and a data D8 written addition ally at the timing t10 is sent to an SO terminal 6 via an output latch 3.
申请公布号 JPS63118967(A) 申请公布日期 1988.05.23
申请号 JP19860265859 申请日期 1986.11.07
申请人 NEC CORP 发明人 KITADA YOSHITAKA
分类号 G06F13/00;G06F13/38;G06F13/42;H04L13/00;H04L25/40;H04L29/08 主分类号 G06F13/00
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