| 摘要 |
<p>A micro processor capable of being connected with a coprocessor is disclosed. The micro processor including an execution unit and a bus control unit coupled to the execution unit. When the execution unit receives an instruction to be executed by the coprocessor, the bus control unit supplies to the coprocessor a command code responsive to the instruction. The micro processor further includes a terminal connected to the execution unit and supplied with a busy signal representing that the coprocessor is in an arithmetic operating state. The execution unit controls the bus control unit to read status information of the coprocessor after the busy signal disappears. The presence or absence of the coprocessor is thus detected from the content of the read status information.</p> |
