| 摘要 |
PURPOSE:To omit the reading decoder and thus to simplify the srtucture of the reading circuit by providing the gate route composed by connection in series the reading gate in plural numbers corresponding to the signal combination code with which the input address signal can be obtained in parallel between each voltage draw-out point and the common terminal. CONSTITUTION:Voltage memory circuit 20 comprises voltage generator circuit 21 connected to power source +V which generates plural different voltage and reading gate unit 22 consisting of gate routes GA0, GA1-GA15which are provided between circuit 21 and common output terminal 23. Then address signal AD of coded plural bits is supplied to each of gate routes GA0, GA1-GA15, and each gate route conducts when signal AD features the proper code contents each. Thus, the voltage corresponding to each gate route itself is delivered to output terminal 23. |
