| 发明名称 |
Data packet multiplexer/demultiplexer |
| 摘要 |
A Multiplexer/Demultiplexer for transmitting packetized data between a processor and a Pulse Code Modulation (PCM) bus. First-in First-Out (FIFO) shift registers, serial-to-parallel and parallel-to-serial converters and associated timing and control circuits are utilized to perform the packetized data transmission.
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| 申请公布号 |
US4744079(A) |
申请公布日期 |
1988.05.10 |
| 申请号 |
US19860913923 |
申请日期 |
1986.10.01 |
| 申请人 |
GTE COMMUNICATION SYSTEMS CORPORATION |
发明人 |
CSAPO, JOHN;SCHLECHTE, GARY L.;WILLIAMS, VICTOR F. |
| 分类号 |
H04L12/64;(IPC1-7):H04J3/24;H04J3/04 |
主分类号 |
H04L12/64 |
| 代理机构 |
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