发明名称 ADDRESS STOPPING CIRCUIT FOR TESTING INSTRUMENT
摘要 PURPOSE:To omit the labor of an operator and at the same time to improve the debugging efficiency by designating an address where a program under debug should be stopped after designating an address where said program must pass through and then stopping a processor. CONSTITUTION:An operator supplies a set signal through a terminal C and transmits signals WE and CS to a stop address setting table 4 via a control circuit 5. Then a setting address is supplied through a terminal B together with a flag setting signal supplied through a terminal D respectively. Therefore the table 4 sets the flag desired by the operator at '1' in an address sent from a receiver 2 and by the set signal received from a receiver 6. Then the operator supplies a set signal to a setting register 8 through a terminal E and sets a flag stage where the processor stops from the receiver 6.
申请公布号 JPS63103337(A) 申请公布日期 1988.05.09
申请号 JP19860248828 申请日期 1986.10.20
申请人 FUJITSU LTD 发明人 FUTAOKU YASUHIRO
分类号 G06F11/28 主分类号 G06F11/28
代理机构 代理人
主权项
地址