Computer system

摘要

A computer system has a first computer (RE1) and a second computer (RE2), which can be connected to a common memory (M) via a multiplexer (MUX). Both computers must be able to access the common memory (M) as required, but the first computer (RE1) must always be able to access it without any delay. For this purpose, a data bus (DB1) of the first computer (RE1) is connected to a pre-decoding logic unit (VD). If this decodes an access demand by the first computer (RE1), it is sent to a memory release logic unit (SFL), which then triggers the multiplexer (MUX) so that the first computer (RE1) is connected to the common memory (M). If no access demand by the first computer (RE1) is decoded, access by the second computer (RE2), which is connected via a demand line (AL) to the memory release logic unit (SFL), is released. On demand from the second computer (RE2), the memory release logic unit (SFL) triggers the multiplexer (MUX) so that the common memory (M) is connected to the second computer (RE2). <IMAGE>