| 摘要 |
PURPOSE:To ensure the correct decoding jobs of data at any phase point by counting the inhibition pulses transmitted at the time point when the frame synchronization is set up between the received signals S1 and S2 and retrieving a frame bit again after converting the phase states of both signals S1 and S2 supplied to a signal point conversion means. CONSTITUTION:A received signal processor RDPU60a counts the inhibition pulses (17) received from a frame synchronizing circuit FSYNC62 via an inhibition pulse counter 80a. Then the RDPU60a changes the values of the central signals C1 and C0 received from the counter 80a every time the inhibition pulses equivalent to one frame (1200 bits) are counted. A signal point converting circuit 70a receives the signals C1 and C2 and converts the input received signal S1 and S2. Thus the frame synchronization is set up and at the same time the unsteadiness of the lock-in phase of a decoder is eliminated. As a result, the data can be correctly received in any phase state with no influence of errors. |
