| 摘要 |
PURPOSE:To decrease the error rate of an identification signal by making the characteristic of a phase detector unchanged with respect to pattern fluctuation of an input signal so as to reduce timing jitter due to the pattern fluctuation of the input signal. CONSTITUTION:A phase error signal detected by an identification circuit 111 and an exclusive OR circuit 112 is selected by a changeover switch circuit 118 while timing information is included in the input signal. Further, when the timing signal is not included in the input signal, the phase error signal by the timing information just before stored and delayed by a delay circuit 119 is selected and even if the pattern of the input signal is fluctuated, the phase comparison characteristic is made unchanged. Thus, the characteristic of the phase detector 11 is not changed against the fluctuation of the input signal, then the fluctuation of locking width of the phase locked loop or jitter is decreased sufficiently due to the pattern fluctuation. |
