发明名称 TRI-STATE CIRCUIT
摘要 PURPOSE:To obtain a tri-state circuit which is reduced in occupation area by decreasing the number of MOS transistors. CONSTITUTION:when an OE signal is at high level, a Q3P is off and the source side of a Q2 P rises to high level; and a Q3N turns off and the source side of a Q1N falls to low level. When a DATA signal is held at low level, the Q1P and Q2P turn on and the Q1N and Q2N turn off, so an output Y falls to low level. Further, when the DATA signal is raised to high level, the Q1P and Q2P turn off and the Q1N and Q2N turn on, so the output Y rises to high level. When the OE signal is held at low level, the Q3P and Q3N both turn on. The gate potential of a Q4P is high in level and the gate potential of a Q4N is low; and the both turn off, so the output Y has high impedance.
申请公布号 JPS6380621(A) 申请公布日期 1988.04.11
申请号 JP19860226998 申请日期 1986.09.24
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 YAMAGUCHI TAKESHI
分类号 H03K19/0175;H03K19/0185;H03K19/094 主分类号 H03K19/0175
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