发明名称 POWER STOPPAGE BACKUP CIRCUIT
摘要 PURPOSE:To realize the backup of a microcomputer at the time of a power stoppage using an inexpensive and simple circuit construction by providing a power stoppage detecting circuit generating a signal simultaneously with the generation of the power stoppage and also generating a restoration signal in a predetermined time after restoring from the power stoppage, and standby mode shifting means for shifting the control part to a standby mode, during the power stoppage. CONSTITUTION:At the time when a power stoppage occurs, an output from a power stoppage detecting circuit 18 is first changed from a low level to a high level, and a microcomputer 9 enters into a standby mode. Slightly later, a second DC power supply 12 falls, and the operation of an oscillation circuit 17 comes to a stop. At the time of restoring to normal power supply, the first DC power supply 12 and a second DC power supply 13 first rise up and power is supplied to the oscillation circuit 17 to start oscillation. Thereafter, the output from the power stoppage detecting circuit 18 rises up after a delay time and generates an interruption in the microcomputer 9, thus slipping out of the stand by mode. This delay time ensures that a stable clock pulse is amply supplied to the microcomputer 9 when it resumes its operation.
申请公布号 JPS6380123(A) 申请公布日期 1988.04.11
申请号 JP19860223130 申请日期 1986.09.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HORIUCHI TOSHIHIRO;OKADA MAKOTO;TAKETSU SHINJI
分类号 F23N5/24 主分类号 F23N5/24
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