| 摘要 |
<p>A timing signal delay circuit which issues input pulse signals while delaying them by a setpoint value that can be adjusted by every predetermined unit, and which can be utilized as a timing generating source for an LSI (semiconductor integrated circuit) tester. The circuit comprises a plurality of delay devices (Dij) that have weighted delay quantities and are arranged in the form of a matrix, a selector (S) which selects a delay device for each array of matrix, means for connecting selected delay devices in series, and an operation control circuit (M) which controls said selector depending upon the setpoint value of delay time and the error quantities of each of the delay devices. Since a delay quantity is given for every predetermined unit despite the error of each of the delay devices, a correction matrix is connected in series with the above matrix, or the weighting of each of the delay devices is modified.</p> |
