| 摘要 |
PURPOSE:To attain a stable shift action by connecting two inverters through two single channel MOS transistors, constituting a memory cell and connecting further through two single channel MOS transistors between the next step memory cells. CONSTITUTION:In a section II, at the section where a clock is H, Nch enhancement type MOS transistors (Nch TRs) 3, 4, 7, 8 and 20 are turned off by AND-OR gates 13 and 14 and an AND gate 15 and Nch TR 19 is turned on by an AND gate 12. In such a case, the information of a memory cell 2 held at the gate capacity of a CMOS inverter 2 is transferred through the Nch TR 19 to the gate capacity of a CMOS inverter 5. When a clock goes to L, the Nch TR 19 is turned off by the AND gate 12, the Nch by TRs 4 and 8 are turned on, therefore, the information of the memory cell 21 transferred to the gate capacity of the CMOS inverter 5 is stored to the gate capacity of a CMOS inverter 6 through the Nch TR 8. In short, the information of the memory cell 21 is shifted by one bit to a memory cell 22. |
