| 摘要 |
PURPOSE:To obtain a DPLL which has fast synchronizing speed by using a device of the same speed level by shifting the phase of a signal by using a delay line. CONSTITUTION:The phase of an input signal fIN is compared by a phase compa rator with that of a signal fout to be outputted to output a down signal when the input signal is advanced in phase or an up signal when delayed. when the up signal is inputted, the contents of an up/down counter 3 increase and when the down signal is inputted, the contents decrease. The output of the up/down counter 3 is inputted as a 3-bit select signal to a multiplexer 2 to select a proper signal specified by the contents of the up/down counter 3 among signals which are delayed in phase, bit by bit, from f1 to f7 after being passed through the delay line 4. Consequently, the signal having the least phase difference is obtained. |
