| 摘要 |
An integrated circuit masterslice (2) in which a plurality of mutually spaced epitaxial columns (4) are formed on an insulative substrate (6). Each column (4) has successive pairs of n-channel FETs (10) alternating with successive pairs of p-channel FETs (8), the contacts of which are accessible by a surface metallization. Drain and source contacts (12, 16, 20, 24) are shared by adjacent FETs, and corresponding elements on adjacent columns are arranged in rows. The masterslice (2) accommodates a wide variety of circuits with a high density transistor grid and interconnect metallization. |
