| 摘要 |
PURPOSE:To improve the data transfer efficiency between buses by providing a register between buses different in data bit width to store both address and data signals. CONSTITUTION:An input/output signal of a MPU 1 is connected to a serial/ parallel converter SPC 3 from a serial port via a serial input/output line 2. The output of the SPC 3 is outputted to a parallel bus line PBUS 5 via a register group 4. A data signal received from the PBUS 5 is connected to a data multiplexer MUX 7 and converted into serial signals by the MUX 7. These serial signals are sent to the MPU 1. A control part 6 consisting of a bus control part 8 and an internal control part 9 controls a group 4 and the MUX 7 to perform the input/output of commands and status signals and also carry out the output or input of output control signals for the group 4 and input signals to the MUX 7 respectively. |
