| 摘要 |
PURPOSE:To improve performance by eliminating the need for clearing other operand to '0' beforehand, and operating the arithmetic for sum up of only one operand of a vector register with a sum arithmetic instruction. CONSTITUTION:A first operand and a second operand are accommodated into a vector register 1. An arithmetic frequency identifying circuit 7, when the sum up arithmetic of only one side operand is executed, identifies whether the action is a first arithmetic action or a second arithmetic action or above. A selecting circuit 2 selects the operand not to execute the sum up arithmetic at the time of the sum up arithmetic of only one side operand or a logic '0'. The operand to execute the sum up arithmetic at the time of executing sum up arithmetic of only one side operand and the output of the selecting circuit 2 are added and outputted by an adder circuit 3. |
