| 摘要 |
PURPOSE:To detect a bus fight at its occurrence point of time by latching a signal on a bus in every bus operation cycle of a processor, comparing it with sent data, detecting the bus fight in case of dissidence and reporting that to the processor. CONSTITUTION:The processor (MPU) 3 latches data on buses 14 and 15 by latch circuits 60 and 70 in every operation cycle where address data and data are generated. Those latched data are compared with data generated in buffers 3a and 3b by the MPU3 by comparing circuits 61 and 71, which send error outputs ER1 and ER2 to the MPU3 as interruption signals when they are not coincident. Then the MPU3 interrupts the operation is response to the interruptions ERs 1 and 2, and fetches and analyzes the data on the buses 14 and 15 in the bus fight state immediately to analyze which bit an error occurs to as the cause of the bus fight, thereby sending the analytic result to a main body 4. |
