发明名称 METHOD AND APPARATUS FOR FRAME SYNCHRONIZATION
摘要 PURPOSE:To facilitate the detection of a frame pattern by extracting a head 1 bit of each subframe, expanding the extracted N-bit into K-series (K is a factor of N), and inserting while dispersing the frame synchronizing bit comprising (N/K)-bit to each series, respectively. CONSTITUTION:One bit is selected from each subframe being 1/N division of one frame and of M-bit constitution, the selected N-bit is expanded into K-set of series (K is a factor of N), and a frame synchronizing pattern comprising N/K-bit is inserted to one series sequentially. Then a cyclic code comprising 1-word N/K-bit of (K-1)-set of series generated from a generation polynomial is inserted sequentially to one of the remaining (K-1)-set series. For example, let N be 14 and K be 2, then a frame pattern in inserted sequentially to a head bit of the subframe of each odd order number while being dispersed by one bit each, and the cyclic code is inserted to the head bit of the subframe of each even order number while being dispersed by one bit each.
申请公布号 JPS6356036(A) 申请公布日期 1988.03.10
申请号 JP19860201042 申请日期 1986.08.26
申请人 NEC CORP 发明人 YOSHIDA TOKUO
分类号 H04J3/06;H04B3/06;H04L7/08 主分类号 H04J3/06
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