| 摘要 |
PURPOSE:To attain the sequence control at a high speed by providing an input/ output control part which can control the input/output part independently in addition to a microprocessor which performs logical decoding. CONSTITUTION:A main operation part 1 includes a logical decoding part 2 containing a microprocessor and the 1st memory part 3. These parts 2 and 3 are connected to each other with an internal bus 7. The part 1 includes a microprocessor 8 different from that of the part 2 and an input/output control part 10 containing the 2nd memory part 9 connected to the processor 8. The part 1 controls an input module 14 of an input/output part 13 and plural output modules 15 via an input/output bus 12. In this case, the part 10 carries out the processing cycle for the (n-1)th output operation or the (n+1)th input operation in parallel to the n-th sequence processing carried out by the part 2. |
