| 摘要 |
PURPOSE:To reduce the hardware quantity and firmware quantity of a controller by inhibiting a leading-zero counting means from counting a leading-zero state when the output signal of a zero register indicates that a word which is high in order than a word inputted to a zero check circuit is not in an all-zero state. CONSTITUTION:The titled processor is provided with an inhibiting means consisting of a data converting circuit 13, etc., which inhibits the leading-zero counting means composed of a leading-zero detecting circuit 8, a leading-zero register 9, an adder, a zero count register 11, etc., from counting the leading-zero state when the output signal of the zero register indicates that the word is not in the all-zero state. The controller needs not decide whether the word higher in order than a word whose leading-zero state is counted is in the all-zero state or not, so the hardware quantity and firmware quantity of the controller are reducible. |
