发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To simply attain the phase synchronization by latching plural pulse trains formed by phase-shifting the phase of an input pulse sequentially in the transition timing of the basic pulse in one direction and selecting one of the plural pulse trains from the result of latch. CONSTITUTION:An input pulse signal being an object to phase synchronization is fed to a delay circuit 1, the phase is shifted sequntially to form plural pulse signal trains (b), (c), (d) having different phase. They are fed to a latch circuit 2 and a gate circuit 3. The latch circuit 2 latches the level of the signals (b)-(d) to DFFs 21-23 in the leading transition timing of the basic pulse (a). Then the gate circuit 3 outputs one pulse train when outputs of the latch circuit 2 corresponding to a pair of pulse trains whose phase are close to each other differ (for example, the signal (b) is outputted if the signals (b), (c) differ).
申请公布号 JPS6331212(A) 申请公布日期 1988.02.09
申请号 JP19860174532 申请日期 1986.07.24
申请人 NEC CORP 发明人 KANEKO HIROMI
分类号 H03K5/00;H03K5/13;H03L7/00 主分类号 H03K5/00
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