发明名称 UNLOCK DETECTION CIRCUIT FOR PLL
摘要 PURPOSE:To detect an unlock in an optimum state and to facilitate the use of a multi-band radio receiver or the like by logic-operating an output from each discrimination circuit and a prescribed data by an arithmetic circuit and detecting the unlock state under the condition according to the result, thereby detecting the unlock state optimizingly. CONSTITUTION:When an unlock detection program is executed, the outputs Q1-Q4 of discrimination circuits 7-10 are sent to a data bus 14 by a control signal TA from an instruction decoder 17 and its content is latched in an A register 18. Then a prescribed data from a ROM 16 is transferred to a B register 19 via a bus 14 by using a control signal TB. With the contents of the outputs Q1-Q4 given shown in figure, when an ALU 15 applies OR operation in the unit of bits from the registers 18, 19 by using a control signal OR, since the output Q2 is logic 1, a signal ALH (=1) representing all 1 is outputted and the unlock state is detected. In selecting a data fed from the ROM 16 to the ALU 15 in this way, the outputs of the circuits 7-10 are discriminated selectively.
申请公布号 JPS6327125(A) 申请公布日期 1988.02.04
申请号 JP19860170636 申请日期 1986.07.18
申请人 SANYO ELECTRIC CO LTD 发明人 OZAWA TOSHIYUKI
分类号 H03L7/18;H03L7/08;H03L7/095 主分类号 H03L7/18
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