| 摘要 |
<p>PURPOSE:To accurately check the initialization of an internal state by observing a power on reset signal from an output terminal for outputting the value of an output latch. CONSTITUTION:The output latch 1 is reset by the inverse signal of a test signal (TES signal) 3 occurring at the time of checking the internal logic of a microcomputer and the logic product (AND) signal 5 of an RES signal 2 occurring at the time of system.resetting inside the microcomputer and set by a reset (PORES) 4 generated from a POR circuit at the rise time of power source voltage VDD and the AND signal 6 of the TES signal 3 and also constituted with a flipflop which can be rewritten with an instruction. In a usual action state since the TES signal 3 is set as '0' even if the VDD rises, the AND 5 is '1' and the AND 6 is '0', so that an output mode register 7 makes a push.pull output circuit 8 in an output inhibition state and an output terminal 9 acts as a usual output terminal which becomes in a high impedance.</p> |
