| 摘要 |
PURPOSE:To execute the processing at a high speed by executing preferentially an output of a register for pipeline of the post-stage, and an output from an operator having a large number of pipeline stages required for an arithmetic operation to the minimum, as for the same computing element, and as for between different computing elements, at the time of competition in case of selecting one of all result outputs. CONSTITUTION:At the time of a selective control of a switching circuit 12, when there is a competition of outputs of the maximum 4 cases of a result of an adder and subtracter circuit system, which is to be executed preferentially is determined, and the degree of priority raises an output of the latest stage on a pipeline. That is, for instance, when a result exists in a register 6 for pipeline of the latest stage, it is executed most preferentially, because unless it is transferred preferentially to an arithmetic operation register 16, the result is lost. Thereafter, by the same way of thinking, the degree of priority is higher in the post-stage side. A switching circuit 13 is also constituted in the same way as the switching circuit 12. |
