| 摘要 |
<p>A technique is taught for accomplishing a read, modify and write operation of a memory (11, 12) in a processor (10) in a single cycle of the processor (10), where a cycle is understood as the time between successive loads of operands to the processor (10). A memory having two distinct portions (11, 12) of operands is provided wherein the single cycle operations are accomplished by virtually addressing the operands in a serpentine or smnae-like configuration. A decoder (20) is provided for efficiently controlling the concurrent reading and writing of operands and controlling the addressing of the memory (11,12).</p> |
