| 摘要 |
PURPOSE:To adjust the timing of latch minutely by selecting a delay time of a clock terminal in response to a switching voltage given to a selector changeover terminal. CONSTITUTION:A changeover terminal A is connected to one input of a NOR circuit 32 and the other input of the NOR circuit 32 is connected to an output of an invert buffer 26. An output of NOR circuits 31, 32 is given to each input of a NOR circuit 33, an output of the NOR circuit 33 is given to an input of an invert buffer 26, a delay clock signal Ca is outputted from an output of the invert buffer 29, and a delay clock signal, the inverse of Ca is outputted from the output of the NOR circuit 33 respectively and fed to respective control gates of transfer gates 11-14. The NOR circuits 31-33 and an invert buffer 34 constitute a selector 30 to apply the selection of changeover of the delay time of the delayed clock signal Ca and the inverse of Ca. |
