发明名称 RECEPTION BUFFER CIRCUIT
摘要 PURPOSE:To contrive to attain miniaturization and low power consumption of the circuit by applying time series multiplex in the unit of bits to a burst data of plural series and parallel input and storing the result in a storage circuit and applying cyclic check to an output signal of the storage circuit. CONSTITUTION:A parallel input plural series burst data are subjected to time series multiplex in the unit of bits at a parallel/serial conversion circuit 1 and inputted to the storage circuit 2 in a reception buffer circuit of a time division multiple access satellite communication system. The circuit 2 receives a write address from an address generating circuit 3 to store an output of the circuit 1 and receives a read address to convert the multiplex data stored in the unit of bits into a burst data form and outputs the result in time series. As a result, a cyclic check circuit 4 applies required cyclic check as to each burst data inputted sequentially. Thus, even if the parallel input number is increased, since one circuit 4 is enough for the check, the processing is executed simply without increasing the circuit scale.
申请公布号 JPS6314531(A) 申请公布日期 1988.01.21
申请号 JP19860158461 申请日期 1986.07.05
申请人 NEC CORP 发明人 TANIGUCHI TAICHI
分类号 H04L1/00;H04B7/212 主分类号 H04L1/00
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