| 摘要 |
PURPOSE:To obtain a vertical output pulse of a constant pulse duration by dividing a stepped doubling clock input synchronizing with the horizontal synchronizing signal of a video signal to a frequency below a vertical frequency to raise the output pulse, at the same time, counting the constant number of the clock inputs and falling the output pulse. CONSTITUTION:When the video signal is inputted to an input terminal 1, the vertical synchronizing signal of the video signal is separated in a synchronizing separator circuit 2 and this vertical synchronizing signal is transferred to a reset circuit 3. This reset circuit 3 resets a frequency divider 5 having the input terminal 4 of the clock pulse synchronizing with the horizontal synchronizing signal of the video signal input by the vertical synchronizing signal. Herein, the frequency of the clock pulse is stepped doubling of the frequency of the horizontal synchronizing signal. The frequency divider 5 counts the clock pulse and divides it to the frequency below the frequency of the vertical synchronizing signal of the video signal input. Thereby, the output pulse stably synchronizing with the video signal input and maintaining the constant pulse duration is obtained. |
