| 摘要 |
PURPOSE:To contrive to improve the utilization efficiency of basic cells by a method wherein a part of the component of the element forming the basic cell is extendedly provided under wirings region between unit macro-system of each logic function and selectively connected to the wiring. CONSTITUTION:The macro-system 14 are formed by means of the basic cell 19 composed of MOSFET's 191-194, and connected to each other. Lateral tracks 221-226 are provided under the wiring region 20 by extended provision of the gate electrode, element of the basic cell 19, and connected to wiring tracks 201, 202,... via connected holes 27. This construction unnecessitates the track occupied by a metallic wiring of the second layer, thus enabling to utilize this track for signal lines etc. connected across the macro-system. The number of metallic wirings of the second layer and of connection holes can be largely reduced. Thus, the occupation factor of the wiring track in the wiring region can be reduced, the intentional decrease of the utilization factor of the basic cell being avoided, and the reliability thus being improved by reducing defectives. |
