| 摘要 |
<p>PURPOSE:To prevent the generation of distortion by providing a control means controlling write/read of a write/read asynchronizing memory and a memory circuit correcting shortage of a receiving PCM signal so as to attain ease of decoding when the received PCM signal and a frame clock of a terminal station device are asynchronous. CONSTITUTION:A marker signal is inserted at each frame to the received PCM signal by data selecting circuits 1, 12 of a buffer circuit and the PCM signal inserted with the marker is written in or read out of an FIFO memory 2 by a clock from 9 write control circuit 3, and a read control circuit 4. Further, the phase of the marker signal read from the memory 2 and the frame phase from a read control circuit 19 are compared by a comparator circuit 16 so as to synchronize the PCM signal with the frame phase. A numeral train inserted to a time slot of the marker is generated from a counter 10 of the buffer circuit and applied to circuits 10, 16. Thus the phase synchronism between the PCM signal and the frame clock is taken easily by the read control circuit 19, FF 20, 21 and a memory circuit 23 or the like so as to decode the PCM signal with no distortion.</p> |
